1. Field of the Invention
The present invention is generally related to Field Effect Transistors, and more specifically to Fin Field Effect Transistors (FinFETs).
2. Description of the Related Art
Over the past few decades, the speed and density of transistors in integrated circuits has continued to increase in accordance with Moore's law, which predicts exponential growth. Consequently, integrated circuits such as microprocessors have delivered greater functionality and performance at a lower cost. As devices on integrated circuits, for example, transistors have become smaller, faster, and cheaper, the use of integrated circuits has become more widespread. Furthermore, the demand for improved performance of integrated circuits continues to grow. As a result, innovative technologies for constructing faster and smaller transistors continue to be developed and adopted.
Fin Field Effect Transistor (FinFET) technology is one such innovative approach to construct high performance transistors on integrated circuits. A FinFET is a double gate structure that is easily manufactured using current fabrication techniques. In a FinFET, a vertical fin is defined to form the body of a transistor. Gates can be formed on one or both sides of the vertical fin. When both sides of the vertical fin have a gate formed thereon, the transistor is generally referred to as a double-gate FinFET. A double-gate FinFET helps suppress short channel effects (SCE), reduce leakage, and enhance switching behavior. Also, a double gate FinFET can increase the electrical width of the transistor, which can in turn increase on-current without increasing the length of the gate conductor.
As circuit densities continue to increase, the length of the fin has continued to decrease in order to scale FinFET devices. One problem with scaling FinFET devices is that the width of a fin is not uniform along the entire length of the fin. The width of the fin may especially deviate from ideal conditions at the ends of the fin, for example. The deviation from ideal fin dimensions may occur along the ends of the fin due to, for example, chip lithographic or etch variations.
Furthermore, as the fin size continues to shrink, the danger of overlaying a gate structure over an irregular area of the fin greatly increases. Variations in the particular area of a fin structure over which a gate structure is formed may occur due to a number of factors such as simple translational displacement between mask levels due to misalignment, optical distortions, magnification errors, and the like. The shrinking of fin length may also increase the probability that a gate structure is formed at or near an end of the fin structure where the fin width is too wide and/or changing along the length of the fin.
In some cases, fin irregularities may result in fin width being different on opposite sides of a gate structure. Consequently, the gate control of the silicon fin may differ between source and drain edges of the gate structure, resulting in degraded and unpredictable electrical behavior. Variations in fin width may also result in variations in threshold voltages and sub-Vt swing.
One solution to the aforementioned problems is to increase fin length, thereby reducing the probability of overlaying a gate structure at or near an end of the fin, where fin width is most likely to be irregular. However, increasing fin length results in increased series resistance along the channel of the FinFET, in addition to decreased device densities on the integrated circuit.
Therefore, there is a need for improved methods for forming FinFETs with short fins of uniform width.